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NCP3011, NCV3011
The master slave identification begins when input voltage
is applied prior to POR. Upon application of input voltage,
the ramp signal. The equation for calculating the remaining
ramp height is shown below:
the device waits for input pulses for a minimum of 40 m s as
shown in Figure 30. During the pulse detection period if
concurrent edges occur on the SYNC pin from an external
V RAMP + VRAMP typ *
F nom
F SYNC
3 1V*
400 kHz
570 kHz
[ 0.70 V
(eq. 3)
source, the device enters slave mode and skips the master
detection sequence. The device will remain in the detected
state until power is cycled.
Current
Sensor
OOV, OUV, and Power Good
The output voltage of the buck converter is monitored at
the Feedback pin of the output power stage. Four
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figures 32 and 33. All comparator outputs are
1.21 V
SYNC_in
SYNC_out
Figure 31.
Master
Detect
&
Hold
GND
SYNC
ignored during the soft ? start sequence as soft ? start is
regulated by the OTA and false trips would be generated.
Further, the Power Good pin is held low until the
comparators are evaluated. After the soft ? start period has
ended, if the feedback is below the reference voltage of
comparator 4 (0.6 < V FB ), the output is considered
“undervoltage,” the device will initiate a restart, and the
Power Good pin remains low with a 55 W pulldown
resistance. If the voltage at the Feedback pin is between the
reference voltages of comparator 4 and comparator 3 (0.60
< V FB < 0.72), then the output voltage is considered “power
not good low” and the Power Good pin remains low. When
the Feedback pin voltage rises between the reference
voltages of comparator 3 and comparator 2 (0.72 < V FB <
0.88), then the output voltage is considered “Power Good”
and the Power Good pin is released. If the voltage at the
External Synchronization
The device can sync to frequencies that are 15% to 60%
higher than the nominal switching frequency. If an external
sync pulse is present at the SYNC pin prior to input voltage
application to the device, then no additional external
components are needed. If the external clock is not present
following power on reset of the device, the voltage on the
SYNC pin will determine whether the device is a master or
a slave. If the external clock source is meant to start after
device operation, its off state should be high or tristate. It is
also important to note that the slope of the internal ramp is
fixed and synchronizing to a faster clock which will truncate
Feedback pin is between the reference voltages of
comparator 2 and comparator 1 (0.88 < V FB < 1.00), the
output voltage is considered “power not good high” and the
power good pin is pulled low with a 55 W pulldown
resistance. Finally, if the feedback voltage is greater than
comparator 1 (1.0 < V FB ), the output voltage is considered
“overvoltage,” the Power Good pin will remain low, and the
device will latch off. To clear a latch fault, input voltage must
be recycled. Graphical representation of the OOV, OUV, and
Power Good pin functionality is shown in Figures 34
and 35.
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